Chyavan Phadke
VLSI and Embedded
About Me
Self-managed and committed to work in a fast-paced environment. Seeking an Internship opportunity to explore and develop professional skills. Efficient in Digital System Design, Verification, Logical Synthesis, Static time Analysis, Physical Design, and Computer Architecture.
- Country USA
- Address San Jose, California
- e-mail [email protected]
- Phone +1 650 680 ****
Education
2020
San Jose State UniversityMS - Electrical Engineering
Embedded Systems | Verilog | System Verilog | UVM | Adv. Comp Architecture | ASIC CMOS Design | SOC Bus Design | Neural Networks
2017
Visvesvaraya Technological UniversityBE - Electronics and Communication
Specilisation in Embedded Ssystems and VLSI
Experience
May 20 - Now
Intel CorporationHardware Intern @intel (Barefoot Networks)
• Hardware Development Intern
Sep 18 - Jan 20
Robert Bosch (RBEI)Embedded Developer (ADAS)
• Implemented vehicle trajectory estimation in curve scenarios for Rear Radar function for Gen5ADAS.
• Managed and coordinated the release cycle by integrating with Jenkins in the continuous integration process.
• Worked closely with the Vehicle Integration team to test and deploy the PCR rear radarfunction.
• Implemented Bird’s EyeView and perception plot in MATLAB and Python
May 17 - Aug 18
Quadrature Innovations Pvt LtdEmbedded Hardware Developer
• Developed two industrial standard products for the irrigation system with 3 phase high voltagesupport.
• Implementing a circuit for voltage regulator, GSM Sim800c, DTMF, SMPS, and relay circuit.
• Designed a Custom 4-layer PCB layout using Altium Designer
Programming Languages
- Hardware: Verilog, Systemverilog, UVM
- Software: C++, Python, Embedded c, TCL
EDA Tools
- 1C Studio (Mentor Graphics), Calibre - DRC/LVS, Cadence Spectre, Synopsys IC Compiler, Synopsys VCS, Synopsys, Primetime, Cadence Encounter, Design Compiler, Cadence Virtuoso
Knowledges
- SPI
- I2C
- CAN,
- UART
- USB
- RS-232
- ZigBee
- InfraRed
- Zynq 7000
- Raspberry pi
- MSP430
- DE10-Lite
- Arduino
- ESP430
- HC-05
- SMPS
- Bluetoooth
Certifications
• SOC Verification Using System Verilog Jun 2020
• Advanced VLSI Design – NTPEL Aug 2020
• Verilog HDL: VLSI Hardware Design Comprehensive Masterclass Sep 2020
• Introduction to VHDL for FPGA and ASIC design Aug 2020
• Cadence - Verilog Language and Application May 2020
• Cadence - System Verilog for Design and Verification Aug 2020
• Introduction to System-on-Chip Design - ARM
Jun 2020
Aug 2020
Sep 2020
Aug 2020
May 2020
Aug 2020
Awards
Winner of Texas Instruments India Innovation Design Contest
Incubate at Indian Institute of Management Bangalore
Videos
How to Make a Homopolar Motor - (Best Science Fair Project)
Light Sensor Using Arduino and LDR
Far Cry 4 Gameplay/Walkthrough Let's Play
Smart wheelchair Presentation
Decimal to 16 bit | 32 bit | 64 bit IEEE 754 Floating Point Representation
DE10-Lite blink program from scratch using Quartus Prime
DIGITAL ALARM CLOCK USING De10 Lite FPGA
IICDC 2016 – Team 1782 Interim Submission
IICDC 2016 – Team 1782 - Quarterfinal Submission – Part 1
IICDC 2016 – Team 1782 - Quarterfinal Submission – Part 2
IICDC 2016
Pre - Finals Video Submission Business Part Team 1782
PCB for IICDC 2016
Pre - Finals Video Submission Technical Part Team code 1782
Pre - Finals Video Submission Technical Part Team 1782
Workout Schedule
Custom Workout PDF file : Open
Squats : 4,10
Leg Press : 3,12
Stiff Legged Deadlift : 4,10
Leg Curl : 3,12
Leg Extension : 3,12
Dumbbell Lunge : 3,8
Leg Press Calf Raises : 3,12
Seated Calf Raises : 3,12
Bench Press : 4,10
Incline Bench Press : 3,12
Cable Crossover : 3,12
Hammer Strength Chest Press : 3,8
Barbell Bicep Curl : 4,10
Rope Cable Hammer Curl : 3,12
Preacher Curl : 3,10
Deadlift : 4,10
Barbell Row : 3,12
Lat Pulldown : 5, 8
Cable Row : 3,12
Pull up : 3,10
Hyperextension : 3,12
Seated Press : 4,10
Lateral Raise : 3,12
Front Raise : 3,12
Barbell Shrugs : 4,12
Dips : 4,10
Rope Tricep Extension : 3, 12
Dumbbell Tricep Extension : 3,12
Blog
Android Apps
Opensource Live Cam
Mount Hamilton, California
